Verification Methodology Manual: Techniques for Verifying HDL Designs. This item is unavailable.Verification Methodology Manual: Techniques for Verifying HDL Designs

This manual has been specifically written for hardware designers that use the Verilog or VHDL hardware description languages to design complex integrated circuits. Whether a designer designs individual circuit modules or complete systems, designers are always faced with the problem of ensuring that the final design is completely free of errors. Achieving design-quality while satisfying budget and time constraints is one of the major objectives for designers in the 21st century. The manual lays the foundation for a methodology based on the effective use of the following front-end design tools and validation techniques. Code and rule checking; Coverage analysis; Test suite analysis; Pre-silicon validation; The manual includes numerous examples of front-end verification techniques using leading-edge HDL verification tools supplied by TransEDA (one of the world's foremost EDA tool vendors). The manual contains a number of case studies and worked examples that together with evaluation copies of TransEDA's verification tools may be downloaded from the World Wide Web for evaluation purposes.