Verification Methodology Manual: Techniques for Verifying HDL Designs

Dempster, David John; Stuart, Michael George; Moses, Chris [Illustrator]

ISBN 10: 0953848213 / ISBN 13: 9780953848218

Published by Teamwork International, 2001

About this Item

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Bibliographic Details

Title: Verification Methodology Manual: Techniques ...

Publisher: Teamwork International

Publication Date: 2001

Binding: Hardcover

Illustrator: Chris Moses

Condition: As New

Edition: 2nd Revised edition.

About this title

Synopsis:

This manual has been specifically written for hardware designers that use the Verilog or VHDL hardware description languages to design complex integrated circuits. Whether a designer designs individual circuit modules or complete systems, designers are always faced with the problem of ensuring that the final design is completely free of errors. Achieving design-quality while satisfying budget and time constraints is one of the major objectives for designers in the 21st century. The manual lays the foundation for a methodology based on the effective use of the following front-end design tools and validation techniques. Code and rule checking; Coverage analysis; Test suite analysis; Pre-silicon validation; The manual includes numerous examples of front-end verification techniques using leading-edge HDL verification tools supplied by TransEDA (one of the world's foremost EDA tool vendors). The manual contains a number of case studies and worked examples that together with evaluation copies of TransEDA's verification tools may be downloaded from the World Wide Web for evaluation purposes.