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VHDL is an IEE standard as well as an ANSI standard language for describing digital designs - but is a large and verbose language with many complex constructs that have complex semantic meaning, and is difficult to understand initially. This primer - updated to include the new standard just released by the IEEE - uses a subset of the language to introduce VHDL to readers at the beginner's level. It explains the complex constructs of the language using an example-based approach.
From the Back Cover:
The power of VHDL-without the complexity!
Want to leverage VHDL's remarkable power without bogging down in its notorious complexity? Get A VHDL Primer, Third Edition. This up-to-the-minute introduction to VHDL focuses on the features you need to get results-with extensive practical examples so you can start writing VHDL models immediately.
Written by Jayaram Bhasker, one of the world's leading VHDL course developers, this best-selling guide has been completely updated to reflect the popular IEEE STD_LOGIC_1164 package. With Bhasker's help, you'll master all these key VHDL techniques:
The book's extensive hardware modeling coverage includes modeling of regular structures, delays, conditional operations, state machines, Moore and Mealy FSMs, clock dividers and much more. You'll find new coverage of text I/O and test benches, as well as complete listings of the IEEE TD_LOGIC_1164 package. J. Bhasker has helped tens of thousands of professionals master VHDL. With A VHDL Primer, Third Edition, it's your turn to succeed.
Title: VHDL Primer, A: Revised Edition
Publisher: Prentice Hall
Publication Date: 1994
Binding: Hardcover
Condition: Very Good
Dust Jacket Condition: No Jacket