VHDL Modeling for Digital Design Synthesis

Language: English

Published by Springer US Jul 1995, 1995

0792395972 / 9780792395973

  • Hardcover
  • New
See all details

Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

5-star seller

AbeBooks seller since January 11, 2012

Hardcover

Condition: New

£ 185.55

£ 19.36 shipping 
Ships from Germany to U.S.A.

Quantity: 2 available

Add to basket
Free 30-day returns

Item description from seller

This item is printed on demand - it takes 3-4 days longer - Neuware -The purpose of this book is to introduce VHSIC Hardware Description Lan guage (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that per mitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the im plementationtechnolo~y. VHDL has data-structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result synthe sis tools accept only subsets of VHDL. This book tries to cover the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum. This book is suitable for working professionals as well as for graduate or under graduate study. Readers can view this book as a way to get acquainted with VHDL and how it can be used in modeling of digital designs. 380 pp. Englisch.…

Seller Inventory # 9780792395973

Title
VHDL Modeling for Digital Design Synthesis
Author
Yu-Chin Hsu
Publisher
Springer US Jul 1995
Publication year
1995
Condition
Neu
Binding
Buch
Language
English
ISBN 10
0792395972
ISBN 13
9780792395973
Item weight
735 grams
Dimensions
241x160x25 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

Shipping rates from Germany to U.S.A.

Item5 to 15 business days5 to 15 business days
First item£ 19.36£ 19.36
Delivery times are set by sellers and vary by carrier and location. Orders passing through Customs may face delays and buyers are responsible for any associated duties or fees. Sellers may contact you regarding additional charges to cover any increased costs to ship your items.

Payment methods

  • Visa
  • Mastercard
  • American Express
  • Apple Pay
  • Google Pay
  • Bank Wire Transfer
  • Check
  • Paypal

Seller's business information

BuchWeltWeit Ludwig Meier e.K.

Germany