Testing Static Random Access Memories
Hamdioui, Said
ISBN 10: 1402077521 ISBN 13: 9781402077524
Published by Springer-Verlag New York Inc., 2004
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About this Item
Description:
Covers testing of one of the important semiconductor memories types. This book addresses testing of static random access memories (SRAMs), both single-port and multi-port. It introduces description of realistic fault models, based on defect injection and SPICE simulation. Series: Frontiers in Electronic Testing. Num Pages: 241 pages, biography. BIC Classification: TJFD5. Category: (P) Professional & Vocational. Dimension: 235 x 155 x 14. Weight in Grams: 520. . 2004. Hardback. . . . . Books ship from the US and Ireland. Seller Inventory # V9781402077524
Synopsis:
Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed.
Features:
-Fault primitive based analysis of memory faults,
-A complete framework of and classification memory faults,
-A systematic way to develop optimal and high quality memory test algorithms,
-A systematic way to develop test patterns for any multi-port SRAM,
-Challenges and trends in embedded memory testing.
Review:
From the reviews:
"Static random access memories (SRAMs) enjoy a strategic position in the microelectronic industry. ... This book concentrates on the study of fault modeling, testing and test strategies for SRAMs. ... The book provides a well-written coverage in the area of single-, two- and n-port SRAM testing, fault modeling, and simulation. It is well-organized and very timely. ... The book promises to make valuable contribution to the education of graduate students ... . I highly recommend this book ... ." (Mile Stojcev, Microelectronics Reliability, Vol. 45, 2005)
"About this title" may belong to another edition of this title.
Bibliographic Details
Title: Testing Static Random Access Memories
Publisher: Springer-Verlag New York Inc.
Publication Date: 2004
Binding: Hardcover
Condition: New
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Testing Static Random Access Memories: Defects, Fault Models and Test Patterns (Frontiers in Electronic Testing, 26)
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Testing Static Random Access Memories
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Gebunden. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Testing Static Random Access Memories covers testing of one of the important semiconductor memories types it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical ackno. Seller Inventory # 4095290
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Testing Static Random Access Memories : Defects, Fault Models, and Test Patterns
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Testing Static Random Access Memories (Hardcover)
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Springer-Verlag New York Inc., New York, NY, 2004
ISBN 10: 1402077521
ISBN 13: 9781402077524
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Hardcover. Condition: new. Hardcover. Embedded memories are one of the fastest growing segments of today's new technology market. According to the 2001 International Technology Roadmap for Semiconductors, embedded memories will continue to dominate the increasing system on chip (SoC) content in the next several years, approaching 94 per cent of the SoC area in about 10 years. Furthermore, the shrinking size of manufacturing structures makes memories more sensitive to defects. Consequently, the memory yield will have a dramatic impact on the overall Defect-per-million level, hence on the overall SoC yield. Meeting a high memory yield requires understanding memory designs, modeling their faulty behaviors, designing adequate tests and diagnosis algorithms as well as efficient self-test and repair schemes. Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it address testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic faul Features: -Fault primitive based analysis of memory faults, -A complete framework of and classification memory faults, -A systematic way to develop optimal and high quality memory test algorithms, -A systematic way to develop test patterns for any multi-port SRAM, -Challenges and trends in embedded memory testing. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Seller Inventory # 9781402077524
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Testing Static Random Access Memories : Defects, Fault Models, and Test Patterns
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Testing Static Random Access Memories
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Springer US, Springer New York Mär 2004, 2004
ISBN 10: 1402077521
ISBN 13: 9781402077524
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Buch. Condition: Neu. Neuware -Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed.Features:Fault primitive based analysis of memory faultsA complete framework of and classification memory faultsA systematic way to develop optimal and high quality memory test algorithmsA systematic way to develop test patterns for any multi-port SRAMChallenges and trends in embedded memory testing.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 244 pp. Englisch. Seller Inventory # 9781402077524
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Testing Static Random Access Memories
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Buch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed. Features: -Fault primitive based analysis of memory faults, -A complete framework of and classification memory faults, -A systematic way to develop optimal and high quality memory test algorithms, -A systematic way to develop test patterns for any multi-port SRAM, -Challenges and trends in embedded memory testing. 244 pp. Englisch. Seller Inventory # 9781402077524
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Testing Static Random Access Memories : Defects, Fault Models And Test Patterns (frontiers In Electronic Testing)
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