Test Resource Partitioning for System-on-a-Chip (Hardcover)

Vikram Iyengar

ISBN 10: 1402071191 / ISBN 13: 9781402071195

Published by Kluwer Academic Publishers, New York, NY, 2002

About this Item

Hardcover. This work explores test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic. SOC integrated circuits composed of embedded cores are commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. This text responds to a pressing need for a structured methodology for SOC test automation.It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume. It aims to pave the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements. Talks about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. This book aims to position test resource partitioning in the context of SOC test automation. It presents various techniques for the partitioning and optimization of the three major SOC test resources. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.

Seller Inventory # 9781402071195

Bibliographic Details

• Title: Test Resource Partitioning for System-on-a-Chip (Hardcover)
• Publisher: Kluwer Academic Publishers, New York, NY
• Publication Date: 2002
• Language: English
• ISBN 10: 1402071191
• ISBN 13: 9781402071195
• Binding: Hardcover
• Condition: new

About this title

Synopsis

Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic.

SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols.

Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume.

Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.