Test Resource Partitioning for System-on-a-Chip

Language: English

Published by Springer US, Springer New York Nov 2012, 2012

1461354005 / 9781461354000

Series: Book 27 of 40 - Frontiers in Electronic Testing

  • Softcover
  • New
See all details

Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

5-star seller

AbeBooks seller since January 11, 2012

Softcover

Condition: New

£ 92.77

£ 19.36 shipping 
Ships from Germany to U.S.A.

Quantity: 2 available

Add to basket
Free 30-day returns

Item description from seller

This item is printed on demand - it takes 3-4 days longer - Neuware -Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into 'virtual sockets' on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic.SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols.Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume.Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements. 248 pp. Englisch.…

Seller Inventory # 9781461354000

Title
Test Resource Partitioning for System-on-a-Chip
Author
Anshuman Chandra
Publisher
Springer US, Springer New York Nov 2012
Publication year
2012
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
1461354005
ISBN 13
9781461354000
Item weight
382 grams
Dimensions
235x155x14 mm
Series
Book 27 of 40: Frontiers in Electronic Testing

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

Shipping rates from Germany to U.S.A.

Item5 to 15 business days5 to 15 business days
First item£ 19.36£ 19.36
Delivery times are set by sellers and vary by carrier and location. Orders passing through Customs may face delays and buyers are responsible for any associated duties or fees. Sellers may contact you regarding additional charges to cover any increased costs to ship your items.

Payment methods

  • Visa
  • Mastercard
  • American Express
  • Apple Pay
  • Google Pay
  • Bank Wire Transfer
  • Check
  • Paypal

Seller's business information

BuchWeltWeit Ludwig Meier e.K.

Germany