From
Books Puddle, New York, NY, U.S.A.
Seller rating 4 out of 5 stars
AbeBooks Seller since 22 November 2018
pp. 392. Seller Inventory # 2698591312
This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’. Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug.
About the Author:
Ashok Mehta is a senior manager in TSMC's CPU/SoC Architecture and Methodology group working on System and 3DIC design projects. In the past, Ashok worked in engineering and management positions at DEC, Data General, Intel and AMCC. He has extensive experience in Design/Verification of complex SoC and Processor devices. He holds nine US patents on ESL and 3DIC designs. Ashok holds a MSEE from University of Missouri.
Title: SystemVerilog Assertions and Functional ...
Publisher: Springer
Publication Date: 2013
Binding: Hardcover
Condition: New
Seller: Blindpig Books, Salt lake city, UT, U.S.A.
hardcover. Condition: Used - Acceptable. 2014. Some light wear. light marking. book slightly rolled. Very readable copy. Seller Inventory # 25-01-28-gw-39561-lcz
Seller: HPB-Red, Dallas, TX, U.S.A.
hardcover. Condition: Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority! Seller Inventory # S_392297209
Seller: SpringBooks, Berlin, Germany
Hardcover. Condition: As New. Unread, like new. Immediately dispatched from Germany. Seller Inventory # CE-2401C-KUECHBODEN-15-1000
Seller: Brook Bookstore On Demand, Napoli, NA, Italy
Condition: new. Questo è un articolo print on demand. Seller Inventory # 6e13a77710d5dfc3aa3821e5f8917034
Quantity: Over 20 available
Seller: moluna, Greven, Germany
Gebunden. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Covers both SystemVerilog Assertions and Sytem Verilog Functional Coverage language and methodologies Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies Explains each c. Seller Inventory # 4199341
Quantity: Over 20 available
Seller: preigu, Osnabrück, Germany
Buch. Condition: Neu. SystemVerilog Assertions and Functional Coverage | Guide to Language, Methodology and Applications | Ashok B. Mehta | Buch | Englisch | 2013 | Springer US | EAN 9781461473237 | Verantwortliche Person für die EU: Springer-Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, productsafety[at]springernature[dot]com | Anbieter: preigu Print on Demand. Seller Inventory # 105903601
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Condition: New. In. Seller Inventory # ria9781461473237_new
Quantity: Over 20 available
Seller: Lucky's Textbooks, Dallas, TX, U.S.A.
Condition: New. Seller Inventory # ABLIING23Mar2716030037183
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Buch. Condition: Neu. Neuware -This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ¿have we functionally verified everything¿. Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug. 392 pp. Englisch. Seller Inventory # 9781461473237
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Buch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug. 392 pp. Englisch. Seller Inventory # 9781461473237