Substrate Noise Coupling in RFICs

Helmy, Ahmed; Ismail, Mohammed

ISBN 10: 1402081650 ISBN 13: 9781402081651
Published by Springer-Verlag New York Inc., 2008
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Series: Analog Circuits and Signal Processing. Num Pages: 134 pages, biography. BIC Classification: TJFC. Category: (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 9. Weight in Grams: 371. . 2008. Hardback. . . . . Seller Inventory # V9781402081651

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Substrate noise coupling in integrated circuits (ICs) is the process by which int- ference signals in the form of voltage and current glitches cause parasitic currents to ?ow in the silicon substrate to various parts of the IC. The source of such glitches and parasitic currents could be from the switching noise of high speed digital clocks on the same chip. In RF and mixed signal ICs the switching noise is coupled to sensitive analog and RF nodes in the IC causing degradation in performance that could severely impact the yield. Thus, overcoming substrate coupling is a key issue in successful “system on chip” ?rst-pass integration where RF and mixed signal blocks, high speed digital I/O interface are integrated with digital signal proce- ing algorithms on the same chip. This is particularly true as we move to sub-90 nanometer system on chip integration. In this book a substrate aware design ?ow is built, calibrated to silicon and used as part of the design and validation ?ows to uncover and ?x substrate coupling problems in RF ICs. The ?ow is used to develop a comprehensive RF substrate noise isolation design guide to be used by RF designers during the ?oor planning, circuit design and validation phases. This will allow designers to optimize the - sign, maximize noise isolation and protect sensitive analog/RF blocks from being degraded by substrate noise coupling.

About the Author: Mohammed Ismail is the Springer Series Advisor for the Analog Circuits and Signal Processing book series

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Bibliographic Details

Title: Substrate Noise Coupling in RFICs
Publisher: Springer-Verlag New York Inc.
Publication Date: 2008
Binding: Hardcover
Condition: New

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Gebunden. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Addresses substrate noise coupling in RF and mixed signal ICs when used in a system on chip(SoC) containing digital ICs as wellGreat reference for courses in RFIC and mixed signal ICs, and for design project coursesReports silicon measureme. Seller Inventory # 4095399

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Buch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The book reports modeling and simulation techniques for substrate noise coupling effects in RFICs and introduces isolation structures and design guides to mitigate such effects with the ultimate goal of enhancing the yield of RF and mixed signal SoCs. The book further reports silicon measurements, and new test and noise isolation structures. To the authors' knowledge, this is the first title devoted to the topic of substrate noise coupling in RFICs as part of a large SoC. 119 pp. Englisch. Seller Inventory # 9781402081651

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Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Substrate noise coupling in integrated circuits (ICs) is the process by which int- ference signals in the form of voltage and current glitches cause parasitic currents to ow in the silicon substrate to various parts of the IC. The source of such glitches and parasitic currents could be from the switching noise of high speed digital clocks on the same chip. In RF and mixed signal ICs the switching noise is coupled to sensitive analog and RF nodes in the IC causing degradation in performance that could severely impact the yield. Thus, overcoming substrate coupling is a key issue in successful 'system on chip' rst-pass integration where RF and mixed signal blocks, high speed digital I/O interface are integrated with digital signal proce- ing algorithms on the same chip. This is particularly true as we move to sub-90 nanometer system on chip integration. In this book a substrate aware design ow is built, calibrated to silicon and used as part of the design and validation ows to uncover and x substrate coupling problems in RF ICs. The ow is used to develop a comprehensive RF substrate noise isolation design guide to be used by RF designers during the oor planning, circuit design and validation phases. This will allow designers to optimize the - sign, maximize noise isolation and protect sensitive analog/RF blocks from being degraded by substrate noise coupling. Seller Inventory # 9781402081651

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