This monograph presents our recent research on Simultaneous Switching Noise (SSN) and related issues for CMOS based systems. Although some SSN related work was previously reported in the literature, it were mainly for Emitter Coupled Logic (ECL) gates using Bipolar Junction Transistors (BJTs). This present work covers in-depth analysis on estimating SSN and its impact for CMOS based devices and systems. At present semiconductor industries are moving towards scaled CMOS devices and reduced supply voltage. SSN together with coupled noise may limit the packing density, and thereby the frequency of operation of packaged systems. Our goal is to provide efficient and yet reliable methodologies and algorithms to estimate the overall noise containment in single chip and multi-chip package assemblies. We hope that the techniques and results described in this book will be useful as guides for design, package, and system engineers and academia working in this area. Through this monograph, we hope that we have shown the necessity of interactions that are essential between chip design, system design and package design engineers to design and manufacture optimal packaged systems. Work reported in this monograph was partially supported by the grant from Semiconductor Research Corporation (SRC Contract No. 92-MP-086).
"Simultaneous Switching Noise (SSN) of CMOS Devices and Systems" covers recent research on package-induced noise problems in single and multi-chip package assemblies. It examines in detail the methods for calculating SSN and overall noise containment in a system. In addition, the authors discuss SSN models and algorithms and a SSN Simulator (SSNS) to calculate the maximum SSN and/or the minimum number of power/ground bon-pad/package-pin connections required for a given system design. These algorithms are extremely powerful in calculating SSN for a large number of output drivers switching simultaneously. Design, package and system engineers will find specific information on a number of important topics and techniques.Among these are: detailed methods of modeling chip-package interface parasitics; SSN modeling for CMOS-based systems, including the negative feedback effects; model development and time-domain signal integrity simulations for signal conductors over a perforated and/or noisy reference plane; total noise budgeting and dynamic noise immunity study for receivers; and, custom CMOS output driver design techniques to minimize package-induced noise.
The result and techniques presented in "Simultaneous Switching Noise of CMOS Devices and Systems" will be useful both to experienced engineers in packaging and systems areas and also to students entering these fields. It will serve as an excellent reference and as a text for advanced courses in CMOS systems design and/or electronic packaging. This book is the first in a new sub-series within SECS. The sub-series is entitled 'Electronic Packaging and Interconnects', and the consulting editor is John L. Prince of the University of Arizona.
