Series: The Springer International Series in Engineering and Computer Science. Num Pages: 214 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 14. Weight in Grams: 514. . 1991. Hardback. . . . .

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Bibliographic Details

Title: Sequential Logic Testing and Verification
Publisher: Kluwer Academic Publishers
Publication Date: 1991
Language: English
ISBN 10: 0792391888
ISBN 13: 9780792391883
Binding: Hardcover
Condition: New

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Synopsis

In order to design and build computers that achieve and sustain high performance, it is essential that reliability issues be considered care� fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the incidence of failure. For instance, in order design reliable inte� gritted circuits, it is necessary to analyze how decisions regarding design rules affect the yield, i.e., the percentage of functional chips obtained by the manufacturing process. Of equal importance in producing reliable computers is the detection of failures in its Very Large Scale Integrated (VLSI) circuit components, caused by errors in the design specification, implementation, or manufacturing processes. Design verification involves the checking of the specification of a design for correctness prior to carrying out an implementation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that there are no manufacturing defects in the integrated circuit. It should be noted that all the above verification mechanisms deal not only with verifying the functionality of the integrated circuit but also its performance.

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