Reduced Instruction Set Computer

Published by VDM Verlag Dr. Müller E.K. Dez 2009, 2009

ISBN 10: 613030806X (ISBN 13: 9786130308063)

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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This item is printed on demand - it takes 3-4 days longer - Neuware -Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online.The acronym RISC, for reduced instruction set computer, represents a CPU design strategy emphasizing the insight that simplified instructions that 'do less' may still provide for higher performance if this simplicity can be utilized to make instructions execute very quickly. Many proposals for a 'precise' definition have been attempted, and the term is being slowly replaced by the more descriptive load-store architecture. Well known RISC families include Alpha, ARC, ARM, AVR, MIPS, PA-RISC, Power Architecture, SuperH, and SPARC. Englisch.

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Bibliographic details

Title
Reduced Instruction Set Computer
Author
Lambert M Surhone
Publisher
VDM Verlag Dr. Müller E.K. Dez 2009
Publication year
2009
Condition
Neu
Binding
Taschenbuch
Item weight
130 grams
Dimensions
22.00x15.00x0.40 cm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

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BuchWeltWeit Ludwig Meier e.K.

Germany