The roots of this book, and of the new research field that it defines, lie in the scaling of VLSI technology. With gigahertz system clocks and ever accelerating design and process innovations, interconnects have become the limiting factor for both performance and density. This increasing impact of interconnects on the system implementation space necessitates new tools and analytic techniques to support the system designer. With respect to modeling and analysis, the response to interconnect dom inance is evolutionary. Atomistic- and grain-level models of interconnect structure, and performance models at multi-gigahertz operating frequencies, together guide the selection of improved materials and process technologies (e. g. , damascene copper wires, low-permittivity dielectrics). Previously in significant effects (e. g. , mutual inductance) are added into performance mod els, as older approximations (e. g. , lumped-capacitance gate load models) are discarded. However, at the system-level and chip planning level, the necessary response to interconnect dominance is revolutionary. Convergent design flows do not require only distributed RLC line models, repeater awareness, unifi cations with extraction and analysis, etc. Rather, issues such as wiring layer assignment, and early prediction of the resource and performance envelope for the system interconnect (in particular, based on statistical models of the system interconnect structure), also become critical. Indeed, system-level interconnect prediction has emerged as the enabler of improved interconnect modeling, more cost-effective system architectures, and more productive design technology.
The design of digital (computer) systems requires several design phases: from the behavioural design, over the logical structural design to the physical design, where the logical structure is implemented in the physical structure of the system (the chip). Due to the ever increasing demands on computer system performance, the physical design phase being one of the most complex design steps in the entire process. The major goal of this book is to develop a priori wire length estimation methods that can help the designer in finding a good lay-out of a circuit in less iterations of physical design steps and that are useful to compare different physical architectures. For modelling digital circuits, the interconnection complexity is of major importance. It can be described by the so called Rent's rule and the Rent exponent."A Priori Wire Length Estimates for Digital Design" will provide the reader with more insight in this rule and clearly outlines when and where the rule can be used and when and where it fails. Also, for the first time, a comprehensive model for the partitioning behaviour of multi-terminal nets is developed.
This leads to a new parameter for circuits that describes the distribution of net degrees over the nets in the circuit. This multi-terminal net model is used throughout the book for the wire length estimates but it also induces a method for the generation of synthetic benchmark circuits that has major advantages over existing benchmark generators.In the domain of wire length estimations, the most important contributions of this work are - a new model for placement optimization in a physical (computer) architecture and the inclusion of the multi-terminal net model in the wire length estimates. The combination of the placement optimization model with Donath's model for a hierarchical partitioning and placement results in more accurate wire length estimates. The multi-terminal net model allows accurate assessments of the impact of multi-terminal nets on wire length estimates. We distinguish between 'delay-related applications,' for which the length of source-sink pairs is important, and 'routing-related applications,' for which the entire (Steiner) length of the multi-terminal net has to be taken into account.
The wire length models are further extended by taking into account the interconnections between internal components and the chip boundary.The application of the models to three-dimensional systems broadens the scope to more exotic architectures and to opto-electronic design techniques. We focus on anisotropic three-dimensional systems and propose a way to estimate wire lengths for opto-electronic systems. The wire length estimates can be used for prediction of circuit characteristics, for improving placement and routing tools in Computer-Aided Design and for evaluating new computer architectures. All new models are validated with experiments on benchmark circuits.
