Title: Principles of Verifiable Rtl Design: A Functional Coding Style Supporting Verification Processes in Verilog
Publisher: Kluwer Academic Publishers
Publication Date: 2000
Language: English
ISBN 10: 0792377885
ISBN 13: 9780792377887
Binding: Hardcover
Condition: Very Good
Dust Jacket Condition: No Jacket

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Synopsis

Explaining how you can write Verilog to describe chip designs at the RT-level in a manner that co-operates with verification processes, this text focuses on how this co-operation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labour costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.

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