Power Efficient Security for IOT Devices

Khaled Tarek

ISBN 10: 6139826098 / ISBN 13: 9786139826094

Published by LAP LAMBERT Academic Publishing, 2019

About this Item

nach der Bestellung gedruckt Neuware - Printed after ordering - The Internet of Things is a novel paradigm that is rapidly gaining ground in the scenario of modern wireless telecommunications. However, security of IoT systems is considered as one of the most important challenges facing system developers. The proposed design is a power adaptive encryption solution that provides four different encryption configurations which are AES-256, AES-192, AES-128, and DES. The IoT device can switch between the four configurations depending on the available power budget for encryption. The design uses Partial Dynamic Reconfiguration (PDR) technology to allow the switching between the four configurations using minimal area and power consumption. The proposed design was tested on a ZedBoard development board after being synthesized using Xilinx Vivado.

Seller Inventory # 9786139826094

Bibliographic Details

• Title: Power Efficient Security for IOT Devices
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2019
• Language: English
• ISBN 10: 6139826098
• ISBN 13: 9786139826094
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 10D millimeters 220 millimeters width by 150 millimeters height by 10 millimeters depth
• Weight: 244 grams

About this title

Synopsis

The Internet of Things is a novel paradigm that is rapidly gaining ground in the scenario of modern wireless telecommunications. However, security of IoT systems is considered as one of the most important challenges facing system developers. The proposed design is a power adaptive encryption solution that provides four different encryption configurations which are AES-256, AES-192, AES-128, and DES. The IoT device can switch between the four configurations depending on the available power budget for encryption. The design uses Partial Dynamic Reconfiguration (PDR) technology to allow the switching between the four configurations using minimal area and power consumption. The proposed design was tested on a ZedBoard development board after being synthesized using Xilinx Vivado.