Performance Evaluation of 3D SRAM Architecture using Coaxial TSV

Language: English

Published by LAP LAMBERT Academic Publishing Jun 2015, 2015

3659746495 / 9783659746499

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This item is printed on demand - Print on Demand Titel. Neuware -3D stacking of logic and memory devices is essential to keep the Moore¿s law ticking. In 3D integration, memory devices can be stacked on the top of processors. TSV based 3D memory architecture enables the reuse of logic dies with multiple memory layers. Conventional 3D memory suffer from speed, power and yield overhead due to large parasitic load of TSV and cross layer PVT variations. In order to overcome these limitations, this paper the physical design of a semi master-slave (SMS) architecture of 3D SRAM which provides a constant-load logic-SRAM interface across various stacked layers and high tolerance for variations in cross-layer PVT is introduced. The SMS scheme is combined with self-timed differential-TSV (STDT) employing a TSV-load tracking scheme to achieve small TSV voltage swing for suppressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads in UMCP designs with scalable stacked layers and wide IO. This provides a universal memory capacity platform.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 68 pp. Englisch.…

Seller Inventory # 9783659746499

Title
Performance Evaluation of 3D SRAM Architecture using Coaxial TSV
Author
R. Arun Prasath
Publisher
LAP LAMBERT Academic Publishing Jun 2015
Publication year
2015
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3659746495
ISBN 13
9783659746499
Item weight
119 grams
Dimensions
220x150x5 mm

buchversandmimpf2000

Emtmannsberg, BAYE, Germany

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