Performance Analysis of Ternary Multiplier using Booth Encoding

Language: English

Published by LAP LAMBERT Academic Publishing Apr 2020, 2020

6202520930 / 9786202520935

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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Softcover

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This item is printed on demand - it takes 3-4 days longer - Neuware -In the world of VLSI, the abundance of battery powered, handy and most importantly high performance electronic devices with inbuilt processors lead us to design the systems that are more robust and efficient enough in terms of the parameters like the design area, the power consumption and the device speed. The high speed data processing, low dissipation of power and smaller area bring with them the requirement of multipliers that are important building blocks of various Digital Signal Processing systems, multimedia applications and computer systems. This dissertation focuses on the design of the multiplier that is based on ternary logic rather than the conventional two valued logic. The 3 bit, 8 bit and 12 bit multipliers have been designed and performance analysis of all the three in terms of power dissipation, delay and area has been done effectively. 84 pp. Englisch.

Seller Inventory # 9786202520935

Title
Performance Analysis of Ternary Multiplier using Booth Encoding
Author
Khushdeep Kaur
Publisher
LAP LAMBERT Academic Publishing Apr 2020
Publication year
2020
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
6202520930
ISBN 13
9786202520935
Item weight
143 grams
Dimensions
220x150x6 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

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BuchWeltWeit Ludwig Meier e.K.

Germany