OPTIMIZATION OF THERMAL AWARE MULTILEVEL ROUTING FOR 3D IC : VLSI PHYSICAL DESIGN

Pandiaraj K

ISBN 10: 6204741314 / ISBN 13: 9786204741314

Published by LAP LAMBERT Academic Publishing, 2022

About this Item

nach der Bestellung gedruckt Neuware - Printed after ordering - Very Large Scale Integration (VLSI) is a process of creating an integrated circuit by linking a large number of transistors into a single chip. A 3D IC provides a positive effect on both execution and wirelength in a power system. A three dimensional integrated circuit would become a developing process where connection delays and power get reduced. The several layers of 3D IC which have been linked could be performed by utilizing through silicon via method. It offers better performance than the conventional approach due to decreased length and power consumption. A test access mechanism technique has become significant owing to the impact of sinking routing cost. If a large number of TSV has been employed, then it leads to superior area consumption and increases ultimate chip cost. Uneven distribution of TSV is occurred owing to the bonding stratum procedure. It affects not only the area but also wirelength and temperature. At the routing phase, through silicon via could be done by identifying whitespace from integrated circuit system.

Seller Inventory # 9786204741314

Bibliographic Details

• Title: OPTIMIZATION OF THERMAL AWARE MULTILEVEL ROUTING FOR 3D IC : VLSI PHYSICAL DESIGN
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2022
• Language: English
• ISBN 10: 6204741314
• ISBN 13: 9786204741314
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 12D millimeters 220 millimeters width by 150 millimeters height by 12 millimeters depth
• Weight: 298 grams

About this title

Synopsis

Very Large Scale Integration (VLSI) is a process of creating an integrated circuit by linking a large number of transistors into a single chip. A 3D IC provides a positive effect on both execution and wirelength in a power system. A three dimensional integrated circuit would become a developing process where connection delays and power get reduced. The several layers of 3D IC which have been linked could be performed by utilizing through silicon via method. It offers better performance than the conventional approach due to decreased length and power consumption. A test access mechanism technique has become significant owing to the impact of sinking routing cost. If a large number of TSV has been employed, then it leads to superior area consumption and increases ultimate chip cost. Uneven distribution of TSV is occurred owing to the bonding stratum procedure. It affects not only the area but also wirelength and temperature. At the routing phase, through silicon via could be done by identifying whitespace from integrated circuit system.