OPTIMIZATION OF THERMAL AWARE MULTILEVEL ROUTING FOR 3D IC

Language: English

Published by LAP LAMBERT Academic Publishing Jan 2022, 2022

6204741314 / 9786204741314

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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This item is printed on demand - it takes 3-4 days longer - Neuware -Very Large Scale Integration (VLSI) is a process of creating an integrated circuit by linking a large number of transistors into a single chip. A 3D IC provides a positive effect on both execution and wirelength in a power system. A three dimensional integrated circuit would become a developing process where connection delays and power get reduced. The several layers of 3D IC which have been linked could be performed by utilizing through silicon via method. It offers better performance than the conventional approach due to decreased length and power consumption. A test access mechanism technique has become significant owing to the impact of sinking routing cost. If a large number of TSV has been employed, then it leads to superior area consumption and increases ultimate chip cost. Uneven distribution of TSV is occurred owing to the bonding stratum procedure. It affects not only the area but also wirelength and temperature. At the routing phase, through silicon via could be done by identifying whitespace from integrated circuit system. 188 pp. Englisch.

Seller Inventory # 9786204741314

Title
OPTIMIZATION OF THERMAL AWARE MULTILEVEL ROUTING FOR 3D IC
Author
Pandiaraj K
Publisher
LAP LAMBERT Academic Publishing Jan 2022
Publication year
2022
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
6204741314
ISBN 13
9786204741314
Item weight
298 grams
Dimensions
220x150x12 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

Shipping rates from Germany to U.S.A.

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First item£ 19.76£ 19.76
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BuchWeltWeit Ludwig Meier e.K.

Germany