3D Networks-on-Chip Architecture Optimization for Low Power Design

Language: English

Published by LAP LAMBERT Academic Publishing Jul 2015, 2015

3659758132 / 9783659758133

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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This item is printed on demand - it takes 3-4 days longer - Neuware -Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This thesis aims at optimizing 3D NoCs by modeling and evaluating alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, novel 3D NoC router architectures and their possible combinations have been investigated with the aim of achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off. This book investigates different heterogeneous 3D NoC architectures which combine 2D and 3D routers to improve area and energy efficiency of 3D NoCs with minimal performance degradation. 180 pp. Englisch.…

Seller Inventory # 9783659758133

Title
3D Networks-on-Chip Architecture Optimization for Low Power Design
Author
Michael Opoku Agyeman
Publisher
LAP LAMBERT Academic Publishing Jul 2015
Publication year
2015
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3659758132
ISBN 13
9783659758133
Item weight
286 grams
Dimensions
220x150x11 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

Shipping rates from Germany to U.S.A.

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BuchWeltWeit Ludwig Meier e.K.

Germany