Motion Estimation Technique for H.264 Advanced Video Coder : Software modeling, hardware architecture design and FPGA implementation of motion estimation block for H.264 AVC

Vikram Arkalgud Chandrasetty

ISBN 10: 3843375992 / ISBN 13: 9783843375993

Published by LAP LAMBERT Academic Publishing, 2010

About this Item

nach der Bestellung gedruckt Neuware - Printed after ordering - Video compression is an active area for potential research. Due to the limitations in the available bandwidth and storage space for high quality multimedia content like - video broadcasting and DVD video data, video compression has become very much necessary to keep up the ever growing demand, yet maintaining the quality in decoded video. Motion Estimation technique in a video coder takes advantage of the temporal redundancy present in video data to achieve substantial compression. The block matching efficiency of the Motion Estimation algorithm, feasibility for hardware implementation and multiple frame storage delays are some of the key challenges faced in implementing a Motion Estimation block. In this work, a software model of Motion Estimation block for H.264 Advanced Video Coder is designed. One Step Search Motion Estimation algorithm is chosen for hardware modeling. The architecture of the model is designed to maximize the throughput of the system by using dual residual energy computation and comparison units for parallel processing of frame data. The hardware model is succesfully implemented and tested on Xilinx Virtex-4 FPGA.

Seller Inventory # 9783843375993

Bibliographic Details

• Title: Motion Estimation Technique for H.264 Advanced Video Coder : Software modeling, hardware architecture design and FPGA implementation of motion estimation block for H.264 AVC
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2010
• Language: English
• ISBN 10: 3843375992
• ISBN 13: 9783843375993
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 5D millimeters 220 millimeters width by 150 millimeters height by 5 millimeters depth
• Weight: 131 grams

About this title

Synopsis

Video compression is an active area for potential research. Due to the limitations in the available bandwidth and storage space for high quality multimedia content like - video broadcasting and DVD video data, video compression has become very much necessary to keep up the ever growing demand, yet maintaining the quality in decoded video. Motion Estimation technique in a video coder takes advantage of the temporal redundancy present in video data to achieve substantial compression. The block matching efficiency of the Motion Estimation algorithm, feasibility for hardware implementation and multiple frame storage delays are some of the key challenges faced in implementing a Motion Estimation block. In this work, a software model of Motion Estimation block for H.264 Advanced Video Coder is designed. One Step Search Motion Estimation algorithm is chosen for hardware modeling. The architecture of the model is designed to maximize the throughput of the system by using dual residual energy computation and comparison units for parallel processing of frame data. The hardware model is succesfully implemented and tested on Xilinx Virtex-4 FPGA.

About the Author

Mr Vikram received B.E. in E&C from Bangalore University (India) and M.Sc[Engg] in VLSI System Design from Coventry University (UK). He is currently pursuing PhD in Computer Systems Engineering at University of South Australia. He was working as Software Engineer at Motorola and Senior Software Engineer at SoftJin Technologies in India.