Low-Noise Low-Power Design for Phase-Locked Loops
Language: English
Published by Springer International Publishing Aug 2016, 2016
- Softcover
- New
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.
AbeBooks seller since January 11, 2012
Condition: New
£ 92.51
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Add to basketItem description from seller
This item is printed on demand - it takes 3-4 days longer - Neuware -This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters. 112 pp. Englisch.
Seller Inventory # 9783319343709
- Title
- Low-Noise Low-Power Design for Phase-Locked Loops
- Author
- Fa Foster Dai
- Publisher
- Springer International Publishing Aug 2016
- Publication year
- 2016
- Condition
- Neu
- Binding
- Taschenbuch
- Language
- English
- ISBN 10
- 331934370X
- ISBN 13
- 9783319343709
- Item weight
- 184 grams
- Dimensions
- 235x155x7 mm
This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.
"Synopsis" may belong to another edition of this title.
About the Author
This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.
Provides detailed introduction to noise reduction techniques for fractional-N phase-locked loop systems;Analyzes the nonlinear effect and its impact on fractional-N phase-locked loop systems;Describes a wide-band integer-N PLL and bandgap reference design for X-band radar application;Explains details of capacitive-coupling techniques for robust quadrature voltage-controlled oscillator (VCO) designs and multi-phase clock generation;Presents basic simulation techniques for quadrature VCO to guarantee robust design."
"About the title" may belong to another edition of this title.
BuchWeltWeit Ludwig Meier e.K.
Bergisch Gladbach, Germany
AbeBooks seller since January 11, 2012
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BuchWeltWeit Ludwig Meier e.K.
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