Logic Synthesis for Finite State Machines Based on Linear Chains of States
Language: English
Published by Springer International Publishing, 2018
Series: Book 102 of 378 - Studies in Systems, Decision and Control
- Softcover
- New
Seller: moluna, Greven, Germanymoluna
AbeBooks seller since July 9, 2020
Condition: New
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Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Presents original synthesis and optimization methods taking into account the peculiarities of a control algorithm and finite state machine (FSM) model in useDiscusses the hardware implementation of control algorithms represented by graph schemes o.
Seller Inventory # 448760121
- Title
- Logic Synthesis for Finite State Machines Based on Linear Chains of States
- Author
- Alexander Barkalov|Larysa Titarenko|Jacek Bieganowski
- Publisher
- Springer International Publishing
- Publication year
- 2018
- Condition
- New
- Binding
- Soft cover
- Language
- English
- ISBN 10
- 3319867148
- ISBN 13
- 9783319867144
- Series
- Book 102 of 378: Studies in Systems, Decision and Control
- Seller catalogs
- Mathematik/Naturwissenschaften/Technik/Medizin
This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation.
This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units
"Synopsis" may belong to another edition of this title.
From the Back Cover
This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation.
This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units
"About the title" may belong to another edition of this title.
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