The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders.
Spot defects are random phenomena present in every fabrication line. As technological processes mature towards submicron features, the effect of these defects on the functional and parametric behaviour of the IC becomes crucial. This work reviews the importance of a defect-sensitivity analysis in contemporary VLSI design processes. The modelling of defects in microelectronics technologies is revised from a set theoretical approach as well as from a practical point of view. This way of handling the material introduces the reader step by step to critical area analysis through the construction of formal mathematical models. The rigorous formalism developed in the book is necessary to study the construction of deterministic algorithms for layout defect exploration. Without this basis, it would be impossible to scan layouts in the order of 1,000,000 objects, or more, in a reasonable time. The theoretical component of this book is complemented with a set of practical case studies for fault extraction, yield prediction and IC defect-sensitivity evaluation.
These case studies emphasize the fact that by suing appropriate formulae combining statistical data with the computed defect-sensitivity, an estimate of the IC's defect tolerance can be obtained at the end of the respective production line. The case studies include a vast range of illustrations depicting critical areas. Examples range from highlighting their geometical nature as a function of the defect size to more specific situations highlighting layout regions where faults may occur. In addition to the visualization of critical areas, numerical data in the form of tables, graphs and histograms are provided for quantification purposes. More than that, ever smarter, defect-tolerant design strategies have to be devised to attain high yields. Obviously, the work presented in the book is not definitive, and more research will always be useful to advance the field of CAD for manufacturability. This is, of course, one of the challenges imposed by the ever-changing nature of microelectronic technologies. CAD developers and yield practitioners from academia and industry should find that this book lays the foundations for further pioneering work.
