Improving Performance and Reducing Power with Hardware Acceleration: Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow
Colin J. Ihrig
From Chiron Media, Wallingford, United Kingdom
Seller rating 5 out of 5 stars
AbeBooks Seller since 2 August 2010
New - Soft cover
Quantity: 10 available
Add to basket