An Improved Markov Random Field Design Approach For Digital Circuits

Hisham Bin Hamid Nor Sagayan Asirvadam Vijanth Anwer Jahanzeb

ISBN 10: 3844332634 / ISBN 13: 9783844332636

Published by VDM Verlag Dr. Mueller Aktiengesellschaft & Co. KG, 2011

About this Item

Print on Demand pp. 88 2:B&W 6 x 9 in or 229 x 152 mm Perfect Bound on Creme w/Gloss Lam.

Seller Inventory # 131690600

Bibliographic Details

• Title: An Improved Markov Random Field Design Approach For Digital Circuits
• Publisher: VDM Verlag Dr. Mueller Aktiengesellschaft & Co. KG
• Publication Date: 2011
• Language: English
• ISBN 10: 3844332634
• ISBN 13: 9783844332636
• Binding: Soft cover
• Condition: New

About this title

Synopsis

As the MOSFET dimensions scale down to nanoscale level, the reliability of circuits based on these devices decreases. Therefore, a mechanism has to be devised that can make the nanoscale systems perform reliably using unreliable circuit components. The solution is fault-tolerant circuit design. Markov Random Field (MRF) is an effective approach that achieves fault-tolerance in integrated circuit design. The previous research on this technique suffers from limitations at the design, simulation and implementation levels. As improvements, the MRF fault-tolerance rules have been validated for a practical circuit example. The simulation framework is extended from thermal to a combination of thermal and random telegraph signal noise sources to provide a more rigorous noise environment for the simulation of nanoscale circuits. Moreover, an architecture-level improvement has been proposed in the design of previous MRF gates. The re-designed MRF is termed as Improved-MRF. By simulating various test circuits in Cadence, it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10 times more noise-tolerant than the CMOS alternatives.

About the Authors

The authors work under the banner of fault-tolerance research group in Universiti Teknologi PETRONAS (UTP). The group is conducting research on various aspects of fault-tolerant circuit design with the support of UTP and MOSTI (Ministry of Science, Technology and Innovation) Malaysia.

The authors work under the banner of fault-tolerance research group in Universiti Teknologi PETRONAS (UTP). The group is conducting research on various aspects of fault-tolerant circuit design with the support of UTP and MOSTI (Ministry of Science, Technology and Innovation) Malaysia.

The authors work under the banner of fault-tolerance research group in Universiti Teknologi PETRONAS (UTP). The group is conducting research on various aspects of fault-tolerant circuit design with the support of UTP and MOSTI (Ministry of Science, Technology and Innovation) Malaysia.