Impact of Spacer Engineering on Performance of Junctionless Transistor

Prabhjot Kaur

ISBN 10: 6139455561 / ISBN 13: 9786139455560

Published by LAP LAMBERT Academic Publishing, 2019

About this Item

nach der Bestellung gedruckt Neuware - Printed after ordering - The scaling of traditional planar CMOS devices is becoming difficult due to increasing gate leakage and subthreshold leakage. Multigate FETs have been proposed to overcome the limitations associated with the scaling of traditional CMOS devices below 100nm region. The multiple electrically coupled gates and the thin silicon body suppress the short-channel effects, thereby lowering the subthreshold leakage current in a multi-gate MOSFET. However, fabrication complexity increases for inversion mode (IM) FinFET devices due to ultra-steep doping profiles requirement. Junctionless transistor (JLT) overcomes the limitations associated with the creation of ultra-steep doping profiles during fabrication and short channel effects. In order to further reduce the SCEs, spacers at the both sides of gate are used that minimizes the leakage current. In this proposed work, JLT is designed with the use of spacer engineering i.e. changing the Lext, spacer's proportion as well as the dielectric values ( ) of spacer material and its performance are evaluated from device characteristics using TCAD software tool.

Seller Inventory # 9786139455560

Bibliographic Details

• Title: Impact of Spacer Engineering on Performance of Junctionless Transistor
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2019
• Language: English
• ISBN 10: 6139455561
• ISBN 13: 9786139455560
• Binding: Taschenbuch
• Condition: Neu

About this title

Synopsis

The scaling of traditional planar CMOS devices is becoming difficult due to increasing gate leakage and subthreshold leakage. Multigate FETs have been proposed to overcome the limitations associated with the scaling of traditional CMOS devices below 100nm region. The multiple electrically coupled gates and the thin silicon body suppress the short-channel effects, thereby lowering the subthreshold leakage current in a multi-gate MOSFET. However, fabrication complexity increases for inversion mode (IM) FinFET devices due to ultra-steep doping profiles requirement. Junctionless transistor (JLT) overcomes the limitations associated with the creation of ultra-steep doping profiles during fabrication and short channel effects. In order to further reduce the SCEs, spacers at the both sides of gate are used that minimizes the leakage current. In this proposed work, JLT is designed with the use of spacer engineering i.e. changing the Lext, spacer's proportion as well as the dielectric values (к) of spacer material and its performance are evaluated from device characteristics using TCAD software tool.