High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Language: English

Published by Springer, 2017

9811010722 / 9789811010729

Series: Book 2 of 13 - Computer Architecture and Design Methodologies

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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH

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Druck auf Anfrage Neuware - Printed after ordering - This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

Seller Inventory # 9789811010729

Title
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
Author
Zheng Wang
Publisher
Springer
Publication year
2017
Condition
Neu
Binding
Buch
Language
English
ISBN 10
9811010722
ISBN 13
9789811010729
Item weight
500 grams
Dimensions
241x160x18 mm
Series
Book 2 of 13: Computer Architecture and Design Methodologies

AHA-BUCH GmbH

Einbeck, Germany

5-star seller

AbeBooks seller since August 14, 2006

Shipping rates from Germany to U.S.A.

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Einbeck, Germany 37574