High Speed Low Offset Power Efficient Dynamic CMOS Comparator

Language: English

Published by LAP LAMBERT Academic Publishing, 2019

6139474736 / 9786139474738

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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH

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Softcover

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nach der Bestellung gedruckt Neuware - Printed after ordering - This book describes various Trade-Offs in Comparator Design especially in Analog & Mixed Signal VLSI Design. The various comparator designs have been illustrated in details with detailed analysis. Further, the analysis and design of a high speed low offset power efficient dynamic CMOS Comparator based on Fully Differential and Double Tail structure is presented. A novel concept of Fully Differential Double Tail Dynamic comparator (FDDTDC) realized with high-speed, low offset with optimized power and area than that of the conventional dynamic comparators is proposed. The end result reveals the potential of new proposed comparator architecture and design methodology for high-speed low offset power efficient applications.

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Bibliographic details

Title
High Speed Low Offset Power Efficient Dynamic CMOS Comparator
Author
Niranjan Devashrayee
Publisher
LAP LAMBERT Academic Publishing
Publication year
2019
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
6139474736
ISBN 13
9786139474738
Item weight
375 grams
Dimensions
220x150x15 mm

AHA-BUCH GmbH

Einbeck, Germany

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AbeBooks seller since August 14, 2006

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