High-Level Verification
Language: English
Published by Springer New York Okt 2014, 2014
- Softcover
- New
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.
AbeBooks seller since January 11, 2012
Condition: New
£ 94.44
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This item is printed on demand - it takes 3-4 days longer - Neuware -Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL. 184 pp. Englisch.…
Seller Inventory # 9781493901012
- Title
- High-Level Verification
- Author
- Sudipta Kundu
- Publisher
- Springer New York Okt 2014
- Publication year
- 2014
- Condition
- Neu
- Binding
- Taschenbuch
- Language
- English
- ISBN 10
- 149390101X
- ISBN 13
- 9781493901012
- Item weight
- 289 grams
- Dimensions
- 235x155x11 mm
"Synopsis" may belong to another edition of this title.
From the Back Cover
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The methodology presented in this book relies upon advances in synthesis techniques, as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically.
The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL.
- Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification;
- Uses a combination of formal techniques to do scalable verification of system designs completely automatically;
- Presents techniques that guarantee properties verified in the high-level design are preserved through the translation to low-levelRTL;
- Written by researchers working in mainstream hardware and software design and includes results from both academia and industry
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"About the title" may belong to another edition of this title.
BuchWeltWeit Ludwig Meier e.K.
Bergisch Gladbach, Germany
AbeBooks seller since January 11, 2012
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