High-Level Verification: Methods and Tools for Verification of System-Level Designs

Language: English

Published by SPRINGER NATURE Mai 2011, 2011

1441993584 / 9781441993588

  • Hardcover
  • New
See all details

Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

5-star seller

AbeBooks seller since January 11, 2012

View this seller's items
Hardcover

Condition: New

£ 94.44

£ 19.71 shipping 
Ships from Germany to U.S.A.

Quantity: 2 available

Add to basket
Free 30-day returns

Item description from seller

This item is printed on demand - it takes 3-4 days longer - Neuware -Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL. 167 pp. Englisch.

Seller Inventory # 9781441993588

Title
High-Level Verification: Methods and Tools for Verification of System-Level Designs
Author
Sudipta Kundu
Publisher
SPRINGER NATURE Mai 2011
Publication year
2011
Condition
Neu
Binding
Buch
Language
English
ISBN 10
1441993584
ISBN 13
9781441993588
Item weight
419 grams
Dimensions
245x164x18 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

Shipping rates from Germany to U.S.A.

Item5 to 15 business days5 to 15 business days
First item£ 19.71£ 19.71
Delivery times are set by sellers and vary by carrier and location. Orders passing through Customs may face delays and buyers are responsible for any associated duties or fees. Sellers may contact you regarding additional charges to cover any increased costs to ship your items.

Payment methods

  • Visa
  • Mastercard
  • American Express
  • Apple Pay
  • Google Pay
  • Bank Wire Transfer
  • Check
  • Paypal

Seller's business information

BuchWeltWeit Ludwig Meier e.K.

Germany