High-Level System Modeling : Specification Languages

Berge, Jean-Michel (EDT); Levia, Oz (EDT); Rouillard, Jacques (EDT)

ISBN 10: 0792396324 / ISBN 13: 9780792396321

Published by Springer, 1995

About this Item

Seller Inventory # 758057-n

Bibliographic Details

• Title: High-Level System Modeling : Specification Languages
• Publisher: Springer
• Publication Date: 1995
• Language: English
• ISBN 10: 0792396324
• ISBN 13: 9780792396321
• Binding: Hardcover
• Condition: New

About this title

Synopsis

A reactive system is one that is in continual interaction with its environment and executes at a pace determined by that environment. Examples of reactive systems are network protocols, air-traffic control systems, industrial-process control systems etc. Reactive systems are ubiquitous and represent an important class of systems. Due to their complex nature, such systems are extremely difficult to specify and implement. Many reactive systems are employed in highly-critical applications, making it crucial that one considers issues such as reliability and safety while designing such systems. The design of reactive systems is considered to be problematic, and p.oses one of the greatest challenges in the field of system design and development. In this paper, we discuss specification-modeling methodologies for reactive systems. Specification modeling is an important stage in reactive system design where the designer specifies the desired properties of the reactive system in the form of a specification model. This specification model acts as the guidance and source for the implementation. To develop the specification model of complex systems in an organized manner, designers resort to specification modeling methodologies. In the context of reactive systems, we can call such methodologies reactive-system specification modeling methodologies.

Synopsis

The process of modelling hardware involves a certain duality: a model may specify and represent the desires and constraints of the designer, or it may imitate something that already exists, and can end in simulation or documentation. One of the main qualities of a specification formalism is its ability to ignore issues that do not belong to this level. Such formalisms are obviously intended for the first stages of a design, but can also be used in the process of redesign. Having a proper level of description thus avoids two symmetric problems: overspecification, which would introduce new instances of the hardware constraints that were only meaningful to the previous ones; and underspecification, which would lead to unnecessary work and sometimes to starting again from scratch. Describing recent progress in specification formalisms in electronic design, this work provides an overview of object-oriented methodologies. It goes on to highlight several formalisms such as VSPEC, ESTELLE, SDL and LOTOS with methods that map their semantics to simulatable or synthesizable VHDL.