High-Level Power Analysis and Optimization (Paperback)

Anand Raghunathan

ISBN 10: 1461374812 / ISBN 13: 9781461374817

Published by Springer-Verlag New York Inc., New York, NY, 2012

About this Item

Paperback. High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level. High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power. High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies. High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.

Seller Inventory # 9781461374817

Bibliographic Details

• Title: High-Level Power Analysis and Optimization (Paperback)
• Publisher: Springer-Verlag New York Inc., New York, NY
• Publication Date: 2012
• Language: English
• ISBN 10: 1461374812
• ISBN 13: 9781461374817
• Binding: Paperback
• Condition: new

About this title

Synopsis

High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level.
High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power.
High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.