Hardware Component Modeling

Oz Levia

ISBN 10: 0792396863 / ISBN 13: 9780792396864

Published by Springer Nature B.V. Mär 1996, 1996

About this Item

Neuware - The VITAL specification addresses the issues of interoperability, backannotation and high performance simulation for sign-off quality ASIC libraries in VHDL. VITAL provides modeling guidelines and a set of pre-defined packages (containing pre-defined routines for modeling functionality and timing) to facilitate the acceleration of designs which use cells from a VITAL library. The VITAL Level-I guidelines constrain the modeling capabilities provided by VHDL in order to facilitate higher performance (Figure I). Accumulating 'gains' Constrained 'flexibility' Higher performance & Increased capacity Benefits Flexibility FujI VHDL 1076 Figure 1: VHDL and VITAL Even within the Level-I guidelines, there are several ways in which a model can be written. In this chapter, we highlight the various modeling trade-offs and provide guidelines which can be used for developing efficient models. We will also discuss the techniques that can be used by tool developers to accelerate the simulation of VIT AL based designs. 2.2. OVERVIEW OF A VITAL LEVEL-l ARCIDTECTURE The VITAL specification is versatile enough to support several modeling styles e.g., distributed delay style, pin-to-pin delay style etc. In general, a VITAL Level-I model can have the structure illustrated in Figure 2.

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Bibliographic Details

• Title: Hardware Component Modeling
• Publisher: Springer Nature B.V. Mär 1996
• Publication Date: 1996
• Language: English
• ISBN 10: 0792396863
• ISBN 13: 9780792396864
• Binding: Buch
• Condition: Neu
• Dimensions: 234W x 156H x 11D millimeters 234 millimeters width by 156 millimeters height by 11 millimeters depth
• Weight: 400 grams

About this title

Synopsis

The VITAL specification addresses the issues of interoperability, backannotation and high performance simulation for sign-off quality ASIC libraries in VHDL. VITAL provides modeling guidelines and a set of pre-defined packages (containing pre-defined routines for modeling functionality and timing) to facilitate the acceleration of designs which use cells from a VITAL library. The VITAL Level-I guidelines constrain the modeling capabilities provided by VHDL in order to facilitate higher performance (Figure I). Accumulating "gains" Constrained "flexibility" Higher performance & Increased capacity Benefits Flexibility FujI VHDL 1076 Figure 1: VHDL and VITAL Even within the Level-I guidelines, there are several ways in which a model can be written. In this chapter, we highlight the various modeling trade-offs and provide guidelines which can be used for developing efficient models. We will also discuss the techniques that can be used by tool developers to accelerate the simulation of VIT AL­ based designs. 2.2. OVERVIEW OF A VITAL LEVEL-l ARCIDTECTURE The VITAL specification is versatile enough to support several modeling styles e.g., distributed delay style, pin-to-pin delay style etc. In general, a VITAL Level-I model can have the structure illustrated in Figure 2.

Synopsis

Highlighting the current status of the modelling of electronic components, this text focuses on four topics: standards, data types, model generation and quality assurance. Three chapters on standards include an introduction to VITAL (an IEEE standard), its application and some of the issues in using and implementing it. Other standards are also covered. One chapter on model generation describes a model generator for reusable component models and another describes a generator which takes actual physical data as its source and which generates a functional model. Two chapters are devoted to improving the quality of models. One introduces a method for quantifying aspects of model quality and the other introduces quality concepts which can lead to an increase in model value through reuse and robustness.