A Handbook on RISC-V System-on-Chip Design : RISC-V Processor Microarchitecture, Interconnect Design, and Hardware/Software Co-Design for Embedded Systems
Language: English
Published by Independently Published Aug 2026, 2026
- Softcover
- New
Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH
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- Title
- A Handbook on RISC-V System-on-Chip Design : RISC-V Processor Microarchitecture, Interconnect Design, and Hardware/Software Co-Design for Embedded Systems
- Author
- James A. Thornton
- Publisher
- Independently Published Aug 2026
- Publication year
- 2026
- Condition
- Neu
- Binding
- Taschenbuch
- Language
- English
- ISBN 13
- 9798190151619
- Item weight
- 840 grams
- Dimensions
- 279x216x19 mm
An instruction set specification tells you what a processor must do. It says almost nothing about how to build one.
That gap is where most engineers stall. The RISC-V ISA is open and well documented, which makes it easy to assume that understanding instruction encoding is the same as being able to design silicon around it. Between the specification and a working chip lie pipeline hazards, cache behaviour, address translation, bus arbitration, interrupt priority, timing closure, power budgets, and a boot sequence that must bring an operating system up on hardware nobody has run before. The reference material for that journey is scattered, and each source presumes the others.
This handbook is the single reference that connects the whole path. Across fourteen chapters it develops a complete RISC-V system-on-chip, beginning with instruction formats and register conventions and ending with a tape-out readiness checklist and a silicon bring-up procedure. Each stage builds on the one before it, so the reasoning behind every design decision stays visible.
Inside this handbook you will:
- Build a five-stage pipeline from a single-cycle baseline, adding forwarding, hazard detection, and branch prediction while tracking cycles per instruction
- Size caches and translation buffers from first principles and predict the effect on average memory access time
- Work through trap entry and exit, control and status registers, physical memory protection, and privilege delegation
- Develop the AXI4 protocol channel by channel, including handshakes, bursts, outstanding transactions, and crossbar arbitration
- Apply verification methodology engineers actually use: testbench architecture, coverage, assertions, linting, and clock domain crossing analysis
- Carry a design from FPGA prototype through ASIC sign-off, then analyse power and the trade-offs that decide whether it ships
- Bring up firmware and boot a kernel on hardware that has never run software before
Coverage runs from the ISA and its extensions, through pipeline construction and hazard resolution, the memory hierarchy and Sv39 virtual memory, the privileged architecture and trap handling, AXI4 interconnect and crossbar design, peripheral and interrupt integration, on-chip debug, verification methodology, FPGA prototyping, ASIC physical implementation, power and performance-area optimisation, and the complete software stack including device tree, bare-metal firmware, a real-time operating system port, and a full Linux boot.
Every chapter opens with learning objectives, develops theory with complete derivations, and closes with practice problems and full solutions. The case study design is a single-hart RV64IMAC core with Sv39 virtual memory, level-one caches, AXI4 interconnect, and a full peripheral set, representative of a real embedded application processor rather than a teaching abstraction.
It is written for practising engineers in embedded systems, digital design, and SoC integration, and for upper-level undergraduate and graduate students who have completed a computer organisation course. It assumes digital logic, basic C, and some assembly familiarity, and no prior knowledge of RISC-V, AXI4, SystemVerilog, or Linux.
Begin at the instruction encoding and follow the design through to first silicon, with every derivation, worked calculation, and practice problem included along the way.
"Synopsis" may belong to another edition of this title.
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