HIGH RESOLUTION AND LOW JITTER FULL CUSTOM ADPLL ARCHITECTURES : FOR FREQUENCY SYNTHESIZER IP

Language: English

Published by LAP LAMBERT Academic Publishing, 2025

6208445582 / 9786208445584

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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH

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nach der Bestellung gedruckt Neuware - Printed after ordering - All digital PLLs are being considered as an effective replacement due to high immunity of digital circuits to PVT variations. However, ADPLLs suffer from the problem of low resolution and high jitter/ phase noise apart from fundamental problems of complex design procedures. It was found through literature surveys and experimental verifications that there are still some challenges related to resolution, jitter/phase noise that need to be addressed, in the existing ADPLLs. Similarly, it was also found that there is a shortcoming in the models used to describe ADPLLs. In this regard, an extensive classification of existing ADPLL architectures was made. Some of the architectures found in literature were critically examined by redesigning and simulation verification at various levels of design with a wide set of simulation/emulation tools. Comparative analysis was done and shortcomings in each architecture were critically identified. Methods to improve resolution and phase noise were proposed and verified using simulation.…

Seller Inventory # 9786208445584

Title
HIGH RESOLUTION AND LOW JITTER FULL CUSTOM ADPLL ARCHITECTURES : FOR FREQUENCY SYNTHESIZER IP
Author
P. Chandra Shekar
Publisher
LAP LAMBERT Academic Publishing
Publication year
2025
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
6208445582
ISBN 13
9786208445584
Item weight
340 grams
Dimensions
220x150x14 mm

AHA-BUCH GmbH

Einbeck, Germany

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AbeBooks seller since August 14, 2006

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