Formal Verification: An Essential Toolkit for Modern VLSI Design
Language: English
Published by Elsevier Science, 2023
- Softcover
- New
Condition: New
£ 102.45
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Covers formal verification algorithms that help users gain full coverage without exhaustive simulation Helps readers understand formal verification tools and how they differ from simulation tools Shows how to create instant testbe.
Seller Inventory # 796215774
- Title
- Formal Verification: An Essential Toolkit for Modern VLSI Design
- Author
- Erik Seligman|Tom Schubert|M .V. Achutha Kiran Kumar
- Publisher
- Elsevier Science
- Publication year
- 2023
- Condition
- New
- Binding
- Soft cover
- Language
- English
- ISBN 10
- 0323956122
- ISBN 13
- 9780323956123
- Edition
- 2nd Edition
Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes.
Every chapter in the second edition has been updated to reflect evolving FV practices and advanced techniques. In addition, a new chapter, Formal Signoff on Real Projects, provides guidelines for implementing signoff quality FV, completely replacing some simulation tasks with significantly more productive FV methods. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity.
- Covers formal verification algorithms that help users gain full coverage without exhaustive simulation
- Helps readers understand formal verification tools and how they differ from simulation tools
- Shows how to create instant testbenches to gain insights into how models work and to find initial bugs
- Presents insights from Intel insiders who share their hard-won knowledge and solutions to complex design problems
"Synopsis" may belong to another edition of this title.
About the Author
Tom Schubert is on the Electrical and Computer Engineering faculty at Portland State University and directs a graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intel's largest pre-silicon validation formal verification team develop and apply FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis.
M V Achutha Kiran Kumar is an Intel Fellow in the Design Engineering group at intel and leads the company’s Formal Verification Central Technology Office, one of the largest industrial Formal Verification teams in the world. He has over 19 years experience where he worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation and various levels of validation including formal verification. He is the co-author of 'Formal Verification - An Essential toolkit for the Hardware Design'.
"About the title" may belong to another edition of this title.
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