Formal Semantics and Proof Techniques for Optimizing VHDL Models

Kothanda Umamageswaran

ISBN 10: 146137331X / ISBN 13: 9781461373315

Published by Springer, Springer New York Okt 2012, 2012

About this Item

This item is printed on demand - Print on Demand Titel. Neuware -Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 184 pp. Englisch.

Seller Inventory # 9781461373315

Bibliographic Details

• Title: Formal Semantics and Proof Techniques for Optimizing VHDL Models
• Publisher: Springer, Springer New York Okt 2012
• Publication Date: 2012
• Language: English
• ISBN 10: 146137331X
• ISBN 13: 9781461373315
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 235W x 155H x 11D millimeters 235 millimeters width by 155 millimeters height by 11 millimeters depth
• Weight: 289 grams

About this title

Synopsis

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.