Formal Semantics and Proof Techniques for Optimizing VHDL Models

Language: English

Published by Kluwer Academic Publishers, 1998

0792383753 / 9780792383758

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Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. Num Pages: 158 pages, biography. BIC Classification: UMX; UYD. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 12. Weight in Grams: 438. . 1998. Hardback. . . . . Books ship from the US and Ireland.

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Title
Formal Semantics and Proof Techniques for Optimizing VHDL Models
Author
Umamageswaran, Kothanda; Pandey, Sheetanshu L.; Wilsey, Philip A.
Publisher
Kluwer Academic Publishers
Publication year
1998
Condition
New
Binding
Hardcover
Language
English
ISBN 10
0792383753
ISBN 13
9780792383758

Kennys Bookstore

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