Formal Semantics and Proof Techniques for Optimizing VHDL Models

Language: English

Published by Springer, Springer New York, 2012

146137331X / 9781461373315

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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH

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Druck auf Anfrage Neuware - Printed after ordering - Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

Seller Inventory # 9781461373315

Title
Formal Semantics and Proof Techniques for Optimizing VHDL Models
Author
Kothanda Umamageswaran
Publisher
Springer, Springer New York
Publication year
2012
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
146137331X
ISBN 13
9781461373315
Item weight
289 grams
Dimensions
235x155x11 mm

AHA-BUCH GmbH

Einbeck, Germany

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AbeBooks seller since August 14, 2006

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