Formal Equivalence Checking and Design Debugging
Language: English
Published by Springer US Jun 1998, 1998
- Hardcover
- New
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.
AbeBooks seller since January 11, 2012
Condition: New
£ 141.57
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Add to basketItem description from seller
This item is printed on demand - it takes 3-4 days longer - Neuware -Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley 252 pp. Englisch. …
Seller Inventory # 9780792381846
- Title
- Formal Equivalence Checking and Design Debugging
- Author
- Kwang-Ting (Tim) Cheng
- Publisher
- Springer US Jun 1998
- Publication year
- 1998
- Condition
- Neu
- Binding
- Buch
- Language
- English
- ISBN 10
- 079238184X
- ISBN 13
- 9780792381846
- Item weight
- 547 grams
- Dimensions
- 241x160x19 mm
- Series
- Book 30 of 40: Frontiers in Electronic Testing
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'
Kurt Keutzer, University of California, Berkeley
"Synopsis" may belong to another edition of this title.
Product Description
"About the title" may belong to another edition of this title.
BuchWeltWeit Ludwig Meier e.K.
Bergisch Gladbach, Germany
AbeBooks seller since January 11, 2012
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