Finite State Machine Datapath Design, Optimization, and Implementation

Language: English

Published by Palgrave Macmillan, 2007

3031797752 / 9783031797750

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nach der Bestellung gedruckt Neuware - Printed after ordering - Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL.Table of Contents: Calculating Maximum Clock Frequency / Improving Design Performance / Finite State Machine with Datapath (FSMD) Design / Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs.

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Title
Finite State Machine Datapath Design, Optimization, and Implementation
Author
Justin Davis
Publisher
Palgrave Macmillan
Publication year
2007
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3031797752
ISBN 13
9783031797750
Item weight
248 grams
Dimensions
235x191x8 mm

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