Fault Tolerant Computer Architecture

Sorin, Daniel

ISBN 10: 3031005953 / ISBN 13: 9783031005954

Published by Springer, Berlin|Springer International Publishing|Morgan & Claypool|Springer, 2009

About this Item

For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore s law into remarkable increases in performance. Recently, however, the.

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Bibliographic Details

• Title: Fault Tolerant Computer Architecture
• Publisher: Springer, Berlin|Springer International Publishing|Morgan & Claypool|Springer
• Publication Date: 2009
• Language: English
• ISBN 10: 3031005953
• ISBN 13: 9783031005954
• Binding: Soft cover
• Condition: New
• Seller catalogs:
  • Mathematik/Naturwissenschaften/Technik/Medizin

About this title

Synopsis

For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore's law into remarkable increases in performance. Recently, however, the bounty provided by Moore's law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it. The two main purposes of this book are to explore the key ideas in fault-tolerant computer architecture and to present the current state-of-the-art - over approximately the past 10 years - in academia and industry. Table of Contents: Introduction / Error Detection / Error Recovery / Diagnosis / Self-Repair / The Future

About the Author

Daniel J. Sorin is an associate professor of Electrical and Computer Engineering and of Computer Science at Duke University. His research interests are in computer architecture, including dependable architectures, verification-aware processor design, and memory system design. He received a PhD and MS in electrical and computer engineering from the University of Wisconsin, and he received a BSE in electrical engineering from Duke University. He is the recipient of an NSF Career Award and a Warren Faculty Scholarship at Duke. He is the author of a previous Synthesis Lecture, Fault Tolerant Computer Architecture