Electrical Design of Through Silicon Via

Through Silicon Via (TSV) is a key technology for realizing three-dimensional integrated circuits (3D ICs) for future high-performance and low-power systems with small form factors. This book covers both qualitative and quantitative approaches to give insights of modeling TSV in a various viewpoints such as signal integrity, power integrity and thermal integrity. Most of the analysis in this book includes simulations, numerical modelings and measurements for verification. The author and co-authors in each chapter have studied deep into TSV for many years and the accumulated technical know-hows and tips for related subjects are comprehensively covered.

Manho Lee received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 2010 and 2012, respectively, where he is currently pursuing the Ph.D. degree in electrical engineering.

His current research interests include the modeling of noise coupling between active circuit and TSV.

Jun So Pak (M'02) received the B.S. degree in electrical communication engineering from Hanyang University, Seoul, Korea, in 1998 and the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2000 and 2005, respectively.

He was a Research Fellow with the High Density Interconnection Group, National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan, in 2005, where he was involved in development of interconnection techniques and interposers for 3-D multichip packaging. Since 2007, he has been a Research Professor with the Department of Electrical Engineering, KAIST. He was the Founder and Director of the 3D-IC Research Center (3DIC- RC) in 2005. His current research interests include development of 3-D stacked chip packaging using through silicon via.

Dr. Pak was a recipient of the Research Fellowship Award from the Japan Society for the Promotion of Science in 2005.

After completing the Ph.D. degree, he joined Picometrix, Inc., Ann Arbor, MI, in 1993, as a Research Engineer, where he was involved in development of pico-second sampling systems and 70-GHz photoreceivers. He joined the Memory Di-vision, Samsung Electronics, Kiheung, Korea, in 1994, where he was engaged in Gbit-scale dynamic random access memory design. He joined the Korea Advanced Institute of Science and Technology (KAIST), Taejon, Korea, in 1996, where he is currently a Professor with the Electrical Engineering and Computer Science Department. At KAIST, his research focuses on modeling, design and measurement methodologies of hierarchical semiconductor systems including high-speed chips, packages, interconnection and multilayer printed circuit boards. Specifically, his major research is focused on chip-package co-design and simulation for signal integrity, power integrity, ground integrity, timing integrity and radiated emission in 3-D semiconductor packages, system-in-packages (SiPs) and system-on-packages. He has successfully demonstrated low-noise and high-performance designs of more than ten SiPs for wireless communication applications, including ZigBee, T-DMB, NFC and UWB. He was on sabbatical leave with Silicon Image, Inc., Sunnyvale, CA, as a Staff Engineer, from 2001 to 2002. He was responsible for low-noise package design of SATA, FC, HDMI and Panel Link SerDes devices. Currently, he is the Director of the Satellite Research Laboratory, Hyundai Motors, Hwaseong-si, Kyungki-do, Korea, for electromagnetic interference and electromagnetic compatibility modeling of automotive RF, power electronic and cabling systems. He has authored or co-authored more than 210 papers in refereed journals and conferences.