Efficient Test Data Compression and Fault Analysis in VLSI Circuits

Language: English

Published by Scholars' Press Mai 2019, 2019

6138834305 / 9786138834304

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This item is printed on demand - Print on Demand Titel. Neuware -In higher order SOC (System On Chip) circuit, designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. In this, testable input data (test data) is generated by using Automatic test pattern generation (ATPG) then it is compressed and compressed data stored to memory. To test the particular circuit that time we will decompress the stored memory test data and then decompressed test data given to the Design Under Test (DUT). Finally DUT fault is tested and identified. It proposes a test compression technique using efficient dictionary selection and bitmask method to significantly reduce the testing time and memory requirements. This algorithm giving a best possible test compression of 92% when compared with other compression methods.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 84 pp. Englisch.…

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Title
Efficient Test Data Compression and Fault Analysis in VLSI Circuits
Author
Sivaganesan Subramaniam
Publisher
Scholars' Press Mai 2019
Publication year
2019
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
6138834305
ISBN 13
9786138834304
Item weight
143 grams
Dimensions
220x150x6 mm

buchversandmimpf2000

Emtmannsberg, BAYE, Germany

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