Digital Logic Design Using Verilog | Coding and RTL Synthesis

Vaibbhav Taraate

ISBN 10: 8132238389 / ISBN 13: 9788132238386

Published by Springer, 2018

About this Item

Digital Logic Design Using Verilog | Coding and RTL Synthesis | Vaibbhav Taraate | Taschenbuch | xxiii | Englisch | 2018 | Springer | EAN 9788132238386 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.

Seller Inventory # 114239991

Bibliographic Details

• Title: Digital Logic Design Using Verilog | Coding and RTL Synthesis
• Publisher: Springer
• Publication Date: 2018
• Language: English
• ISBN 10: 8132238389
• ISBN 13: 9788132238386
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 235W x 155H x 23D millimeters 235 millimeters width by 155 millimeters height by 23 millimeters depth
• Weight: 743 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make ita useful read for students and hobbyists. 

About the Author

Vaibbhav Taraate is Entrepreneur and Mentor at "Semiconductor Training @ Rs.1". He holds a BE (Electronics) degree from Shivaji University, Kohlapur in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his MTech (Aerospace Control and Guidance)  in 1999 from IIT Bombay. He has over 15 Years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.