Digital Design Through Verilog

Vishwajit Barbuddhe

ISBN 10: 620078308X / ISBN 13: 9786200783080

Published by LAP LAMBERT Academic Publishing Mär 2020, 2020

About this Item

Neuware -The book contains: Introduction to Verilog HDL: Verilog as HDL, Levels of Design Description, Concurrency, Simulation and Synthesis, Programming Language Interface, Module. Language Constructs and Conventions: Introduction, Keywords, Identifiers, White Space, Characters, Comments, Numbers, Strings, Logic Values, Data Types, Scalars and Vectors, Operators. Gate Level Modeling: Introduction, And Gate Primitive, Module Structure, Other Gate Primitives, Illustrative Examples, Tristate Gates, Array of Instances of Primitives, Design of Flip-Flops with Gate Primitives, Gate Delay, Strengths and Contention Resolution, Net Types. Modeling at Data-flow Level: Introduction, Continuous Assignment Structure, Delays and Continuous Assignments, Assignment to Vector, Operators. Behavioral Modeling: Introduction, Operations and Assignments, 'Initial' Construct, Always construct, Assignments with Delays, 'Wait Construct', Design at Behavioral Level, Blocking and Non-blocking Assignments, The 'Case' Statement, 'If' and 'if-Else' Constructs, 'Assign-De-Assign' Constructs, 'Repeat' Construct, for loop, 'The Disable' Construct, 'While Loop', Forever Loop, sequential and Parallel Blocks.Books on Demand GmbH, Überseering 33, 22297 Hamburg 76 pp. Englisch.

Seller Inventory # 9786200783080

Bibliographic Details

• Title: Digital Design Through Verilog
• Publisher: LAP LAMBERT Academic Publishing Mär 2020
• Publication Date: 2020
• Language: English
• ISBN 10: 620078308X
• ISBN 13: 9786200783080
• Binding: Taschenbuch
• Condition: Neu

About this title

Synopsis

The book contains: Introduction to Verilog HDL: Verilog as HDL, Levels of Design Description, Concurrency, Simulation and Synthesis, Programming Language Interface, Module. Language Constructs and Conventions: Introduction, Keywords, Identifiers, White Space, Characters, Comments, Numbers, Strings, Logic Values, Data Types, Scalars and Vectors, Operators. Gate Level Modeling: Introduction, And Gate Primitive, Module Structure, Other Gate Primitives, Illustrative Examples, Tristate Gates, Array of Instances of Primitives, Design of Flip-Flops with Gate Primitives, Gate Delay, Strengths and Contention Resolution, Net Types. Modeling at Data-flow Level: Introduction, Continuous Assignment Structure, Delays and Continuous Assignments, Assignment to Vector, Operators. Behavioral Modeling: Introduction, Operations and Assignments, 'Initial' Construct, Always construct, Assignments with Delays, 'Wait Construct', Design at Behavioral Level, Blocking and Non-blocking Assignments, The 'Case' Statement, 'If' and 'if-Else' Constructs, 'Assign-De-Assign' Constructs, 'Repeat' Construct, for loop, 'The Disable' Construct, 'While Loop', Forever Loop, sequential and Parallel Blocks.