This book assumes no previous knowledge of digital design. You start at the beginning learning about basic gates, logic equations, Boolean algebra, and Karnaugh maps. In over 75 examples we show you how to design digital circuits using Verilog and simulate and synthesize them using Xilinx's free development environment, Vivado HL WebPACK. You can synthesize the designs to a Xilinx Spartan3E FPGA on either the BASYS™ system board that can be purchased from Digilent, Inc (www.digilentinc.com) or any of the Nexys boards. More recently, Digilent offers the Nexys4 board with an Artix-7 FPGA. To synthesize your designs to a Xilinx FPGA you will need to download the Vivado WebPACK from Xilinx, Inc. (www.xilinx.com). You can use Adept 2.1 to download your bit files to either the BASYS2, Nexys2, or Nexys3 boards. The Nexys4 board uses iMPACT to configure the FPGA which is included with Vivado WebPACK. All references to the BASYS board in this book apply to the BASYS2 board. All of the user constraints (.ucf) and Xilinx Design Constraints (.xdc) files for each board can be downloaded from http://www.lbebooks.com/downloads.htm.

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