Designing 2D and 3D Network-on-Chip Architectures

Tatas, Konstantinos; Siozios, Kostas; Soudris, Dimitrios; Jantsch, Axel

ISBN 10: 1493945505 / ISBN 13: 9781493945504

Published by Springer, 2016

About this Item

PRINT ON DEMAND pp. 278.

Seller Inventory # 18378092111

Bibliographic Details

• Title: Designing 2D and 3D Network-on-Chip Architectures
• Publisher: Springer
• Publication Date: 2016
• Language: English
• ISBN 10: 1493945505
• ISBN 13: 9781493945504
• Binding: Soft cover
• Condition: New

About this title

Synopsis

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

From the Back Cover

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty. Case studies are used to illuminate new design methodologies.

· Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect;

· Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance;

· Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management.