Designing 2D and 3D Network-on-Chip Architectures

Konstantinos Tatas, et al.

ISBN 10: 1461442737 / ISBN 13: 9781461442738

Published by Springer-Verlag Publishing, 2013

About this Item

Fine/As New; Semi-Flexible Covers; This book is brand new and still sealed in the publisher's original shrinkwrap; Perfect, new condition; This book will be stored and delivered in a sturdy cardboard box with foam padding; Medium Format (8.5" - 9.75" tall); Red and purple covers with title in white lettering; 2013, Springer-Verlag Publishing; 265 pages; "Designing 2D and 3D Network-on-Chip Architectures," by Konstantinos Tatas, et al.

Seller Inventory # SKU-W17HA02112229

Bibliographic Details

• Title: Designing 2D and 3D Network-on-Chip Architectures
• Publisher: Springer-Verlag Publishing
• Publication Date: 2013
• Language: English
• ISBN 10: 1461442737
• ISBN 13: 9781461442738
• Binding: Hardcover
• Condition: Like New

About this title

Synopsis

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

From the Back Cover

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty. Case studies are used to illuminate new design methodologies.

· Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect;

· Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance;

· Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management.